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RNA51958A,B
Voltage Detecting, System Resetting IC Series
REJ03D0915-0100 Rev.1.00 Mar 02, 2009
Description
RNA51958A,B are semiconductor integrated circuits for resetting of all types of logic circuits such as CPUs, and has the feature of setting the detection voltage by adding external resistance. They include a built-in delay circuit to provide the desired retardation time simply by adding an external capacitor. They fined extensive applications, including battery checking circuit, level detecting circuit and waveform shaping circuit.
Features
* * * * * Few external parts Large delay time with a capacitor of small capacitance (td 100 ms, at 0.33 F) Wide supply voltage range: 2 V to 17 V Wide application range Ordering Information
Part Name RNA51958AFPH0 RNA51958BFPH0 Package Type SOP-8 pin SOP-8 pin Package Code PRSP0008DE-C PRSP0008DE-C Package Abbreviation FP FP Taping Abbreviation (Quantity) H (2,500 pcs / Reel) H (2,500 pcs / Reel) Surface Treatment 0 (Ni/Pd/Au) 0 (Ni/Pd/Au)
Application
* Reset circuit of Pch, Nch, CMOS, microcomputer, CPU and MCU, Reset of logic circuit, Battery check circuit, switching circuit back-up voltage, level detecting circuit, waveform shaping circuit, delay waveform generating circuit, DC/DC converter, over voltage protection circuit
Recommended Operating Condition
* Supply voltage range: 2 V to 17 V
Outline and Article Indication
* RNA51958A, B
Type No.
R958A YMWC CCC
SOP-8
R958B YMWC CCC
Pin No.1 Trace Code
Lot No. Y : Year Code (the last digit of year) M : Month Code W : Week Code C : Control Code
REJ03D0915-0100 Rev.1.00 Mar 02, 2009 Page 1 of 11
RNA51958A,B
Pin Arrangement
RNA51958AFP/BFP
NC 1 Input 2 NC 3 GND 4 (Top view) NC: No Connection
8 NC 7 Power-supply 6 Output 5 Delay capacitor
Outline: PRSP0008DE-C
Block Diagram
RNA51958A, B Powersupply A: Built-in Load B: Open Collector
5A Typ Input - + 1.25V +
25A Typ
Output
GND
Delay capacitor
Operating Waveform
RNA51958A, B
Input voltage
1.25V
t H
td td
Output state
L
td 0.34 x Cd(pF) s
t
REJ03D0915-0100 Rev.1.00 Mar 02, 2009 Page 2 of 11
RNA51958A,B
Absolute Maximum Ratings
(Ta = 25C, unless otherwise noted)
Item Supply voltage Output sink current Output voltage Power dissipation Thermal derating Operating temperature Storage temperature Input voltage range Symbol VCC Isink VO Pd K Topr Tstg Vin Ratings 18 6 VCC 18 400 4.4 -40 to +85 -55 to +125 -0.3 to VCC -0.3 to +7 Unit V mA V mW mW/C C C V VCC 7 V VCC > 7 V Conditions
Type A (output with constant current load) Type B (open collector output) 8-pin SOP (PRSP0008DE-C) Refer to the thermal derating curve. 8-pin SOP (PRSP0008DE-C)
Electrical Characteristics
(Ta = 25C, unless otherwise noted) * "H" reset type
Item Detecting voltage Hysteresis voltage Detecting voltage temperature coefficient Supply voltage range Input voltage range Input current Circuit current Delay time Output saturation voltage Output leakage current Output load current Output high voltage Symbol VS VS VS/T VCC Vin Iin ICC tpd Vsat IOH IOC VOH Min 1.20 9 -- 2 -0.3 -0.3 -- -- -- 1.6 -- -- -40 VCC-0.2 Typ 1.25 15 0.01 -- -- -- 100 390 360 3.4 0.2 -- -25 VCC-0.06 Max 1.30 23 -- 17 VCC 7.0 500 590 540 7.0 0.4 30 -17 -- Unit V mV %/C V V nA A ms V nA A V VCC 7V VCC > 7V Vin = 1.25V VCC = 5V Test Conditions
Type A, VCC = 5V Type B, VCC = 5V
Cd = 0.01F * VCC = 5V, Vin < 1.35V, Isink = 4mA
Type B Type A, VCC = 5V, VO = 1/2 x VCC Type A
Note:
Please set the desired delay time by attaching capacitor of the range between 4700 pF and 10 F.
REJ03D0915-0100 Rev.1.00 Mar 02, 2009 Page 3 of 11
RNA51958A,B
Typical Characteristics
Thermal Derating 500 Detection Voltage vs. Ambient Temperature 1.28
Power Dissipation Pd (mW)
Detection Voltage VS (V)
400 300 200 100 0 0
8-pin SOP (PRSP0008DE-C)
1.27
VSH
1.26 1.25 1.24 1.23 1.22 -40 -20
VSL
25
50
75 85 100
125
0
20
40
60
80 100
Ambient Temperature Ta (C)
Ambient Temperature Ta (C)
Detection Voltage vs. Supply Voltage 1.28 250
Input Current vs. Supply Voltage
VIN = 1.25V
Detection Voltage VS (V)
Input Current IIN (nA)
1.27 1.26 1.25
VSL VSH
200 150
Ta = -40C
100
Ta = 25C
1.24 1.23 1.22 0
50 0 0
Ta = 85C
4
8
12
16
20
4
8
12
16
20
Supply Voltage VCC (V)
Supply Voltage VCC (V)
Delay Capacitance vs. Delay Time
Delay Time vs. Ambient Temperature 6
CD = 0.01F
Delay Capacitance Cd (F)
10 7V CC = 5V 5 3 1 7 5 3 0.1 7 5 3 0.01 7 5 3 0.001 0.1 3 57 1 3 5 7 10 3 5 7 100 3 5 7 1000
Delay Time tpd (ms)
5 4
VCC = 5V
3 2 1 0 -40 -20
10V VCC = 15V
0
20
40
60
80 100
Delay Time tpd (ms)
Ambient Temperature Ta (C)
REJ03D0915-0100 Rev.1.00 Mar 02, 2009 Page 4 of 11
RNA51958A,B
Canstant Current at Cd pin vs. Ambient Temperature Output Saturation Voltage vs. Output Sink Current 0.3
Supply voltage detecting : VCC = 5V
Canstant Current at Cd pin Ipd (A)
-12 -10 -8 -6 -4 -2 0 -40 -20
VCC = 5V VCC = 15V
Output Saturation Voltage Vsat (V)
0.2
0.1
0
20
40
60
80 100
0 0
1
2
3
4
5
6
Ambient Temperature Ta (C)
Output Sink Current Isink (mA)
Output Load Current vs. Output Voltage (RNA51958A)
Circuit Current vs. Supply Voltage (RNA51958B) 800
Ta = -40C
Output Load Current ICC (A)
Circuit Current ICC (A)
-40
-30
VCC = 5V VCC = 10V VCC = 15V
600
-20
400
Ta = 25C Ta = 85C
-10
200
0 0
4
8
12
16
0 0
4
8
12
16
Output Voltage VO (V)
Supply Voltage VCC (V)
REJ03D0915-0100 Rev.1.00 Mar 02, 2009 Page 5 of 11
RNA51958A,B
Example of Application Circuit
Reset Circuit of RNA51958
VCC
R1 Input
Powersupply Output RNA51958x
RL
Powersupply RESET Logic circuit GND
R2
GND
Delay capacitor Cd
Figure 1 Reset Circuit of RNA51958 Notes: 1. When the detecting supply voltage is 4.25 V, RNA51953 are used. In this case, R1 and R2 are not necessary. When the voltage is anything except 4.25 V, RNA51957 and RNA51958 are used. In this case, the detecting supply voltage is 1.25 x (R1 +R2)/R2 (V) approximately. The detecting supply voltage can be set between 2 V and 15 V. 2. If a longer delay time is necessary, RNA51953, RNA51957, RNA51958 are used. In this case, the delay time is about 0.34 x Cd (pF) s. 3. If the RNA51958 and the logic circuit share a common power source, type A (built-in load type) can be used whether a pull-up resistor is included in the logic circuit or not. 4. The logic circuit preferably should not have a pull-down resistor, but if one is present, add load resistor RL to overcome the pull-down resistor. 5. When the reset terminal in the logic circuit is of the low reset type, RNA51953 and RNA51957 are used and when the terminal is of the high reset type, RNA51958 are used. 6. When a negative supply voltage is used, the supply voltage side of RNA51958 and the GND side are connected to negative supply voltage respectively. Case of Using Reset Signal except Supply Voltage in the RNA51958
(a) Reset at ON
Powersupply RNA51958x R2 GND Delay capacitor Cd Control signal Powersupply RESET Logic circuit GND VCC R1 Input
(b) Reset at transistor ON
Powersupply RNA51958x R2 GND Delay capacitor Cd Powersupply RESET Logic circuit GND VCC
R1 Input
Out put
RL
Out put
RL
Figure 2 Case of Using Reset Signal except Supply Voltage in the RNA51958
REJ03D0915-0100 Rev.1.00 Mar 02, 2009 Page 6 of 11
RNA51958A,B Delay Waveform Generating Circuit When RNA51958 are used, a waveform with a large delay time can generate only by adding a small capacitor.
Power-supply
R1
Input RNA51958
R2
Output
GND
Delay capacitor Cd
Figure 3 Delay Waveform Generating Circuit
Operating Waveform
Input (VCC partial pressure)
Output
td
td 0.34 x Cd(pF) s
Figure 4 Operating Waveform
REJ03D0915-0100 Rev.1.00 Mar 02, 2009 Page 7 of 11
RNA51958A,B
Notice for use
About the Power Supply Line 1. About bypass capacitor Because the ripple and the spike of the high frequency noise and the low frequency are superimposed to the power supply line, it is necessary to remove these. Therefore, please install C1 and C2 for the low frequency and for the high frequency between the power supply line and the GND line as shown in following figure 5.
VCC
+
C1
C2 R1 Input Vin R2 GND
Power-supply Output RNA51958 Delay capacitor Cd
Example of ripple noise measures
Figure 5 Example of Ripple Noise Measures 2. The sequence of voltage impression Please do not impress the voltages to the input terminals earlier than the power supply terminal. Moreover, please do not open the power supply terminal with the voltage impressed to the input terminal. (The setting of the bias of an internal circuit collapses, and a parasitic element might operate.) About the Input Terminal 1. Setting range of input voltage The following voltage is recommended to be input to the input terminal (pin 2). about 0.8 (V) < Vin < VCC - 0.3 (V) ... at VCC 7 V about 0.8 (V) < Vin < 6.7 (V) ............. at VCC > 7 V 2. About using input terminal Please do an enough verification to the transition characteristic etc. of the power supply when using independent power supply to input terminal (pin 2).
VCC Vin is decided to the VCC subordinating, and operates in the range about 0.8 (V) < Vin < VCC - 0.3 (V). Output
Power-supply Input Vin GND RNA51958
Delay capacitor Cd
Figure 6 Recommended Example
REJ03D0915-0100 Rev.1.00 Mar 02, 2009 Page 8 of 11
RNA51958A,B
Independent
VCC1
VCC2 Power-supply Independent Input Vin
VCC
VCC Power-supply Output RNA51958 GND Delay capacitor Cd
Input Vin GND RNA51958
Output
Delay capacitor Cd
GND
Example 1. Independent power supply system Please do enough verifying about transition characteristic of VCC1 and VCC2.
Example 2. Logic pulse input (not recommended)
Figure 7 3. Calculation of detecting voltage Detecting voltage Vs can be calculated by the following expression. However, the error margin is caused in the detecting voltage because input current Iin (standard 100 nA) exists if it sets too big resistance. Please set the constant to disregard this error margin. R1 + R 2 VS = 1.25 x + Iin x R1 R2 error margin
VCC
R1 Vin R2 Iin Input GND
Power-supply Output RNA51958 Delay capacitor Cd
Figure 8 Influence of Input Current 4. About the voltage input outside ratings Please do not input the voltage outside ratings to the input terminal. An internal protection diode becomes order bias, and a large current flows.
REJ03D0915-0100 Rev.1.00 Mar 02, 2009 Page 9 of 11
RNA51958A,B Setting of Delay Capacity Please use capacitor Cd for the delay within the range of 10 F or less. When a value that is bigger than this is set, the problem such as following (1), (2), and (3) becomes remarkable.
t
VCC Output
tpd
tPHL
Figure 9 Time Chart at Momentary Voltage-Decrease (1) The difference at delay time becomes remarkable. A long delay setting of tens of seconds is fundamentally possible. However, when set delay time is lengthened, the range of the difference relatively grows, too. When a set value is assumed to be `tpd', the difference occurs in the range from 0.47 x tpd to 2.05 x tpd. For instance, 34 seconds can be calculated at 100 F. However, it is likely to vary within the ranges of 16-70 seconds. (2) Difficulty to react to a momentary voltage decrease. For example, the reaction time tPHL is 10 s when delay capacitor Cd = 0.1 F. The momentary voltage-decrease that is longer than such tPHL are occurs, the detection becomes possible. When the delay capacitance is enlarged, tPHL also becomes long. For instance, it becomes about 100 to 200 s in case of circuit constant C1 = 100 F. (Characteristic graph 1 is used and extrapolation in case of Cd = 100 F.) Therefore, it doesn't react to momentary voltage-decrease that is shorter than this. (3) Original delay time is not obtained. When the momentary voltage-decrease time `t' is equivalent to tPHL, the discharge becomes insufficient and the charge starts at that state. This phenomenon occurs at large capacitance. And, original delay time tpd is not obtained. Please refer to characteristic graph 2. (Delay time versus input pulse width)
Characteristic Graph 1 Reaction Time vs. Delay Capacitance (Example data) 1000 Characteristic Graph 2 Delay Time vs. Momentary Voltage Decrease Pulse Width (Example data) 10000
Delay Capacitance 0.01F 0.033F 0.1F 0.33F 1F 2.2F 3.3F
Reaction Time tPHL (s)
200 100
Delay Time tpd (ms)
0.1 1 10 Delay Capacitance Cd (F) 100
1000
100
10
10
1 0.01
1 1
10
1000 100 Pulse Width (s)
10000
Figure 10 Characteristic Graph
REJ03D0915-0100 Rev.1.00 Mar 02, 2009 Page 10 of 11
RNA51958A,B Setting of Output Load Resistance (RNA51958B) High level output voltage can be set without depending on the power-supply voltage because the output terminal is an open collector type. However, please guard the following notes. 1. Please set it in value (2 V to 17 V) within the range of the power-supply voltage recommendation. Moreover, please never impress the voltage of maximum ratings 18 V or more even momentarily either. 2. Please set output load resistance (pull-up resistance) RL so that the output current (output inflow current IL) at L level may become 4 mA or less. Moreover, please never exceed absolute maximum rating (6 mA).
VCC (2V to 17V) RL 6 IL 4mA
Figure 11 Output Load Resistance RL
Others 1. Notes when IC is handled are published in our reliability handbook, and please refer it. The reliability handbook can be downloaded from our homepage (following URL). http://www.renesas.com/fmwk.jsp?cnt=reliability_root.jsp&fp=/products/common_info/reliability 2. Additionally, please inquire of our company when there is an uncertain point on use.
Package Dimensions
JEITA Package Code P-SOP8-4.4x4.85-1.27 RENESAS Code PRSP0008DE-C Previous Code -- MASS[Typ.] 0.1g
*1
D
F
8
5
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
*2
HE
E
Index mark
Terminal cross section ( Ni/Pd/Au plating )
1 Z e 4
*3
c
Reference Symbol
Dimension in Millimeters
bp
x
M L1
A1
L
y
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
A
A2
Min Nom Max 4.65 4.85 5.05 4.2 4.4 4.6 1.85 0.00 0.1 0.20 2.03 0.34 0.4 0.46 0.15 0.20 0.25 0 8 5.7 6.2 6.5 1.12 1.27 1.42 0.12 0.10 0.75 0.25 0.45 0.65 0.90
REJ03D0915-0100 Rev.1.00 Mar 02, 2009 Page 11 of 11
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